The present invention relates to semiconductor integrated circuits, and in particular to very large scale semiconductor integrated circuits (referred to in the following as VLSIs) which have a large chip size and which utilize a high clock signal frequency in order to enhance processing operations of a microprocessor etc.
As semiconductor technology has advanced in recent years, the number of elements and the chip size of large semiconductor integrated circuits have continually increased. This is especially true in the case of VLSIs which include a microprocessor and a built-in cache memory. Furthermore as a result of improvements in device technology, the operating speeds of circuit elements, such as logic elements, have increased. Hence, the frequency of the clock signal used in operation of such circuit elements has also increased in recent years. Such an increase in the clock signal frequency enables the processing capability of a microprocessor to be enhanced. However problems arise in the design of a VLSI having a microprocessor and a cache memory, when a high frequency of clock signal is used, i.e. problems arise relating to timing deviations of the clock signal in different regions of the semiconductor integrated circuit. These deviations result from variations in the path lengths over which the clock signal is supplied to various regions of the integrated circuit, with these path lengths depending upon the respective positions of various circuit elements. Variations in clock signal phase throughout the integrated circuit thereby arise, such variations generally being referred to as a skew of the clock signal supplied to different elements. If for example a logic circuit within an integrated circuit produces output data at a certain time point, and the data are to be received simultaneously by two other logic circuits, then if there is clock skew it is possible that one circuit will receive the data at the appropriate time but that the other circuit may receive incorrect data at that time. This problem of clock skew is particularly serious in the case of a VLSI, due to the large chip size, so that errors in logic circuit operation can readily arise.
In the prior art, a clock signal supply circuit is generally positioned near the outer periphery of an integrated circuit chip (where the term "clock signal supply circuit" as used herein designates a circuit which produces a clock signal that is then supplied to various regions of an integrated circuit). If this is done, and if for example the clock signal supply circuit is positioned near the right-side edge of the integrated circuit chip, then the larger is the size of the chip, the greater will become the deviations in connecting lead capacitance and connecting lead resistance of the connecting leads that supply the clock signal to circuit elements at the right and left-hand sides of the integrated circuit chip. Differences in the amount of delay of the clock signal supplied to these elements in different positions on the chip will thereby arise, i.e. clock signal phase deviations (clock skew) will occur. Furthermore if a 2-phase non-overlap clock signal is used, then it is necessary to ensure that the non-overlap period of that clock signal is maintained. However if the maximum value of the clock skew of the clock signal supplied to respectively different logic circuits becomes greater than this non-overlap period, then operating errors will occur.